The present invention generally relates to an information processing apparatus improving a memory access. More specifically, the present invention is directed to an information processing apparatus capable of quickly defining a real address used to retrieve a cache memory, which is translated by a translation look-aside buffer from a logical address obtained by employing a general-purpose register from an instruction, capable of retrieving the cache memory at an earlier stage, and capable of continuing a process of the instruction at a high efficiency.
U.S. Pat. No. 5,148,538 issued to Celtruda et al., discloses a logical address/real address translation to access a cache memory.
FIG. 1 is a schematic block diagram for representing one example of an information processing apparatus which has been designed by the Applicants during a process approaching to the present invention. In FIG. 1, reference numeral 110 indicates an instruction register containing an index register identifier 101, a base register identifier 102, and displacement bits 103; reference numeral 120 represents a large number of general-purpose registers (will be referred to "GPR" hereinafter) usable as an index register and a base register; reference numeral 130 shows an address adder for generating a logical address having a page address portion and a page offset portion based upon a content 221 of an index register, a content 222 of a base register, and the displacement bits 103; and reference numeral 140 denotes a logical address register for storing a logical address obtained by the address adder 130. Furthermore, reference numeral 140 shows a logical address register for storing a logical address obtained by the address adder 130; reference numeral 150 is a translation look-aside buffer (will be referred to "TLB" hereinafter) for selecting a real address corresponding to a logical address from the logical address register 140; reference numeral 160 indicates a real address register for storing a page address portion of the real address obtained from the TLB 150 and a page offset portion from the logical address register 140; reference numeral 170 denotes a cache memory apparatus for retrieving storage data based on the real address from the real address register 160 and for supplying the data to a requesting apparatus; reference numeral 171 shows a cache memory; reference numeral 172 represents a cache directory for judging whether or not data demanded by an instruction is present; and reference numeral 180 indicates an arithmetic and logical unit (will be called as "ALU" hereinafter).
A process of an instruction such as a register data load instruction as shown in FIG. 2 with employment of a memory operand will be performed as follows:
First, a machine cycle for decoding an instruction is performed.
In FIG. 2, assuming now that symbol "OP" indicates "LOAD", in case that it is required to load operands designated by X.sub.2 /B.sub.2 /D.sub.2 to R1, an instruction stored in the instruction register 110 is decoded, an identifier 101 of this index register X2 and an identifier 102 of a base register B2 are transferred to the GPR 120 respectively. The GPR 120 is arranged by, for instance, 16 general-purpose register groups, to which identification numbers defined from 0 to 15 have been allocated. The GPR 120 selects the general-purpose register having the identification number corresponding to the index register identifier 101, and transfers the content of this selected general-purpose register to the address adder 130 as a content 221 of the index register. Also, the GPR 120 selects the general-purpose register having the identification number corresponding to the base register identification 102, and transfers the content of this selected general-purpose register as a content 222 of the base register to the address adder 130.
In this case, when a 0th general-purpose register is designated as the numbers for the index register and the base register, data of an all-zero output is transferred to the address adder 130 irrelevant to the content of the 0th general-purpose register.
In the subsequent machine cycle of the logical address generation, the address adder 130 adds the content 221 of the index register, the content 222 of the base register, and the displacement bit 103, as illustrated in FIG. 3, to obtain the logical address, and then a process for storing this value into the logical address register 140 is executed.
During the next TLB retrieval machine cycle, the following process is executed.
The TLB 150 is retrieved under such a condition that the page address portion of the logical address register 140 is used as a key, and then the TLB 150 transfers the page address portion of the real address corresponding to this logical address to the real address register 160. Thereafter, both of the page address portion of the real address from the TLB 150, and the page offset portion from the logical address register 140 are stored into the real address register 160.
It should be noted that since a detailed description about the retrieval of the TLB 150 is not directly related to the technical spirit and scope of the present invention, further explanation is omitted.
The below-mentioned process will now be executed in the machine cycle for the next cache memory retrieving operation.
The cache memory apparatus 170 retrieves a cache directory 172 by way of the real address derived from the real address register 160, and judges whether or not the data demanded by the instruction is present in the cache memory 171. If the data is not located within the cache memory 171, the cache memory apparatus 170 does not directly retrieve the data from the cache memory 171, and transfers the demanded data to another independent mechanism in which this demanded data is retrieved. To the contrary, if there is the demanded data in the cache memory 171, then the cache memory apparatus 170 retrieves the data from the cache memory 171 based upon the real address, and transfers the data demanded by the instruction to the ALU 180.
In the next machine cycle of the calculation execution, the ALU 180 performs the calculation based upon the data which has been transferred from the cache memory apparatus 170.
To achieve a quick definition of the real address required for retrieving the cache memory apparatus, it is necessary to reconsider such a problem. That is to say, 3 machine cycles are continuously required to store an instruction into the instruction register, to decode the instruction, to generate the logical address, to access the TLB, and then to define the real address required for reading out the memory operand demanded by this instruction.